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1/32 february 2002 m95040 m95020, m95010 4/2/1 kbit serial spi bus eeprom with high speed clock features summary n compatible with spi bus serial interface (positive clock spi modes) n single supply voltage: C 4.5v to 5.5v for m950x0 C 2.5v to 5.5v for m950x0-w C 1.8v to 3.6v for m950x0-s n 5 mhz clock rate (maximum) n status register n byte and page write (up to 16 bytes) n self-timed programming cycle n adjustable size read-only eeprom area n enhanced esd protection n more than 1,000,000 erase/write cycles n more than 40 year data retention figure 1. packages so8 (mn) 150 mil width pdip8 (bn) 0.25 mm frame 8 1 tssop8 (dw) 169 mil width 8 1
m95040, m95020, m95010 2/32 summary description the m95040 is a 4 kbit (512 x 8) electrically eras- able programmable memory (eeprom), access- ed by a high speed spi-compatible bus. the other members of the family (m95020, m95010) are identical, though proportionally smaller (2 and 1 kbit, respectively). each device is accessed by a simple serial interface that is spi-compatible. the bus signals are c, d and q, as shown in table 1 and figure 2. the device is selected when chip select (s ) is tak- en low. communications with the device can be interrupted using hold (hold ). write instruc- tions are disabled by write protect (w ). figure 2. logic diagram figure 3. dip connections figure 4. so and tssop connections table 1. signal names ai01789c s v cc m95xxx hold v ss w q c d c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground d v ss c hold q sv cc w ai01790c m95xxx 1 2 3 4 8 7 6 5 1 ai01791c 2 3 4 8 7 6 5 d v ss c hold q sv cc w m95xxx
3/32 m95040, m95020, m95010 signal description v cc must be held within the specified range: v cc (min) to v cc (max). all of the input and output signals can be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in tables 12 to 16). these sig- nals are described next. serial data output (q) this output signal is used to transfer data serially out of the device. data bytes are shifted out on the falling edge of the serial clock (c). serial data input (d) this input signal is used to transfer data serially into the device. instructions, addresses, and input data bytes are shifted in on the rising edge of the serial clock (c). serial clock (c) this input signal provides the timing for the serial interface. chip select (s ) when this input signal is high, the device is dese- lected, and the serial data output (q) is high im- pedance. hold (hold ) this input signal is used to pause temporarily any serial communications with the device, without los- ing bits that have already been passed on the se- rial bus. write protect (w ) this input signal is used to control whether the memory is write protected. when w is held low, writes to the memory are disabled, but other oper- ations remain enabled. no action on this signal, or on the write enable latch (wel) bit, can interrupt a write cycle that has already started. connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 5 shows three devices, connected to an mcu, on a spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, all the others being high impedance. figure 5. bus master and memory devices on the spi bus note: 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. ai03746d bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold
m95040, m95020, m95010 4/32 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: C cpol=0, cpha=0 C cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 6, is the clock polarity when the bus master is in stand-by mode and not transferring data: C c remains at 0 for (cpol=0, cpha=0) C c remains at 1 for (cpol=1, cpha=1) figure 6. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
5/32 m95040, m95020, m95010 operating features power-up when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s ) must be al- lowed to follow the v cc voltage. it must not be al- lowed to float, but should be connected to v cc via a suitable pull-up resistor. as a built in safety feature, chip select (s ) is edge sensitive as well as level sensitive. after power- up, the device does not become selected until a falling edge has first been detected on chip select (s ). this ensures that chip select (s ) must have been high, prior to going low to start the first op- eration. power-down at power-down, the device must be deselected. chip select (s ) should be allowed to follow the voltage applied on v cc . active power and stand-by power modes when chip select (s ) is low, the device is en- abled, and in the active power mode. the device consumes i cc , as specified in tables 12 to 16. when chip select (s ) is high, the device is dis- abled. if an erase/write cycle is not currently in progress, the device then goes in to the stand-by power mode, and the device consumption drops to i cc1 . hold condition the hold (hold ) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are dont care. to enter the hold condition, the device must be selected, with chip select (s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the de- vice while it is in the hold condition, has the effect of resetting the state of the device, and this mech- anism can be used if it is required to reset any pro- cesses that had been in progress. the hold condition starts when the hold (hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 7). the hold condition ends when the hold (hold ) signal is driven high at the same time as serial clock (c) already being low. figure 7 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. figure 7. hold condition activation ai02029d hold c hold condition hold condition
m95040, m95020, m95010 6/32 status register figure 8 shows the position of the status register in the control logic of the device. this register con- tains a number of control bits and status bits, as shown in table 2. bits b7, b6, b5 and b4 are always read as 1. wip bit. the write in progress bit is a volatile read-only bit that is automatically set and reset by the internal logic of the device. when set to a 1, it indicates that the memory is busy with a write cy- cle. wel bit. the write enable latch bit is a volatile read-only bit that is set and reset by specific in- structions. when reset to 0, no write or wrsr instructions are accepted by the device. bp1, bp0 bits. the block protect bits are non- volatile read-write bits. these bits define the area of memory that is protected against the execution of write cycles, as summarized in table 3. table 2. status register format b7 b0 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bit write in progress bit
7/32 m95040, m95020, m95010 data protection and protocol control to help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. the main security measures can be summarized as follows: C the wel bit is reset at power-up. Cchip select (s ) must rise after the eighth clock count (or multiple thereof) in order to start a non- volatile write cycle (in the memory array or in the status register). C accesses to the memory array are ignored dur- ing the non-volatile programming cycle, and the programming cycle continues unaffected. C invalid chip select (s ) and hold (hold ) transi- tions are ignored. for any instruction to be accepted and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) that latches the last bit of the instruction, and before the next rising edge of serial clock (c). for this, the last bit of the instruction can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (ex- cept in the case of rdsr and read instructions). moreover, the "next rising edge of clock" might (or might not) be the next bus transaction for some other device on the bus. when a write cycle is in progress, the device pro- tects it against external interruption by ignoring any subsequent read, write or wrsr instruc- tion until the present cycle is complete. table 3. write-protected block size status register bits protected block array addresses protected bp1 bp0 m95040 m95020 m95010 0 0 none none none none 0 1 upper quarter 180h - 1ffh c0h - ffh 060h - 7fh 1 0 upper half 100h - 1ffh 80h - ffh 040h - 7fh 1 1 whole memory 000h - 1ffh 00h - ffh 000h - 7fh
m95040, m95020, m95010 8/32 memory organization the memory is organized as shown in figure 8. figure 8. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
9/32 m95040, m95020, m95010 instructions each instruction starts with a single-byte code, as summarized in table 4. if an invalid instruction is sent (one not contained in table 4), the device automatically deselects it- self. table 4. instruction set note: 1. a8 = 1 for the upper half of the memory array of the m95040, and 0 for the lower half, and is dont care for other devices. 2. x = dont care. figure 9. write enable (wren) sequence write enable (wren) the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 9, to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) being driven high. instruc tion description instruction format wren write enable 0000 x110 wrdi write disable 0000 x100 rdsr read status register 0000 x101 wrsr write status register 0000 x001 read read from memory array 0000 a 8 011 write write to memory array 0000 a 8 010 c d ai01441d s q 2 1 34567 high impedance 0 instruction
m95040, m95020, m95010 10/32 figure 10. write disable (wrdi) sequence write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 10, to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) be- ing driven high. the write enable latch (wel) bit, in fact, be- comes reset by any of the following events: C power-up C wrdi instruction execution C wrsr instruction completion C write instruction completion C write protect (w ) line being held low. c d ai03790d s q 2 1 34567 high impedance 0 instruction
11/32 m95040, m95020, m95010 figure 11. read status register (rdsr) sequence read status register (rdsr) one of the major uses of this instruction is to allow the mcu to poll the state of the write in progress (wip) bit. this is needed because the device will not accept further write or wrsr instructions when the previous write cycle is not yet finished. as shown in figure 11, to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte are then shifted in, on serial data input (d). the current state of the bits in the status register is shifted out, on serial data out (q). the read cycle is terminated by driving chip select (s ) high. the status register may be read at any time, even during a write cycle (whether it be to the memory area or to the status register). all bits of the sta- tus register remain valid, and can be read using the rdsr instruction. however, during the current write cycle, the values of the non-volatile bits (bp0, bp1) become frozen at a constant value. the updated value of these bits becomes avail- able when a new rdsr instruction is executed, af- ter completion of the write cycle. on the other hand, the two read-only bits (write enable latch (wel), write in progress (wip)) are dynamically updated during the on-going write cycle. the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register in- struction is accepted. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status regis- ter (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the rele- vant memory area (as defined in table 3) be- comes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protect- ed mode has not been set. c d s 2 1 3456789101112131415 instruction 0 ai01444d q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m95040, m95020, m95010 12/32 figure 12. write status register (wrsr) sequence write status register (wrsr) this instruction has no effect on bits b7, b6, b5, b4, b1 and b0 of the status register. as shown in figure 12, to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and data byte are then shifted in on serial data input (d). the instruction is terminated by driving chip se- lect (s ) high. chip select (s ) must be driven high after the rising edge of serial clock (c) that latch- es the eighth bit of the data byte, and before the the next rising edge of serial clock (c). if this con- dition is not met, the write status register (wrsr) instruction is not executed. the self- timed write cycle starts, and continues for a peri- od t w (as specified in tables 17 to 20), at the end of which the write in progress (wip) bit is reset to 0. the instruction is not accepted, and is not execut- ed, under the following conditions: C if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) C if a write cycle is already in progress C if the device has not been deselected, by chip select (s ) being driven high, after the eighth bit, b0, of the data byte has been latched in C if write protect (w ) is low. c d ai01445b s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
13/32 m95040, m95020, m95010 figure 13. read from memory array (read) sequence note: d epending on the memory size, as shown in table 5, the most significant address bits are dont care. read from memory array (read) as shown in figure 13, to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address byte are then shifted in, on serial data input (d). the most significant address bit, a8, is incorporated as bit b3 of the instruction byte, as shown in table 4. the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is automatically incre- mented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruc- tion. the read cycle is terminated by driving chip se- lect (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut- ed, if a write cycle is currently in progress. table 5. address range bits read from memory array (read) as shown in figure 13, to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the ad- dress is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is automatically incre- mented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruc- tion. the read cycle is terminated by driving chip se- lect (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut- ed, if a write cycle is currently in progress. c d ai01440d s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 76543 2 0 1 high impedance data out instruction byte address 0 device m95040 m95020 m95010 address bits a8-a0 a7-a0 a6-a0
m95040, m95020, m95010 14/32 figure 14. byte write (write) sequence note: d epending on the memory size, as shown in table 5, the most significant address bits are dont care. write to memory array (write) as shown in figure 14, to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip se- lect (s ) high after the rising edge of serial clock (c) that latches the last data bit, and before the next rising edge of serial clock (c) occurs any- where on the bus. in the case of figure 14, this oc- curs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in tables 17 to 20), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s ) continues to be driven low, as shown in figure 15, the next byte of input data is shifted in. in this way, all the bytes from the given address to the end of the same page can be programmed in a single instruction. if chip select (s ) still continues to be driven low, the next byte of input data is shifted in, and is used to overwrite the byte at the start of the current page. the instruction is not accepted, and is not execut- ed, under the following conditions: C if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) C if a write cycle is already in progress C if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the rising edge of serial clock (c) that latches the last data bit, and before the next ris- ing edge of serial clock (c) occurs anywhere on the bus) C if write protect (w ) is low or if the addressed page is in the region protected by the block pro- tect (bp1 and bp0) bits. ai01442d c d s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 23 high impedance instruction byte address 0 765432 0 1 data byte
15/32 m95040, m95020, m95010 figure 15. page write (write) sequence note: d epending on the memory size, as shown in table 5, the most significant address bits are dont care. c d s 2 1 345678910111213141516171819 20 21 22 23 instruction byte address 0 data byte 1 c d ai01443d s 26 25 27 28 29 30 31 8+8n 24 data byte 16 9+8n 10+8n 11+8n 12+8n 13+8n 14+8n 15+8n 136 137 138 139 140 141 142 143 data byte n 76 3210 54 data byte 2 7 a7 a6 a5 a4 a3 a2 a1 a0 a8 765432 0 1 7 6543210765432 0 1
m95040, m95020, m95010 16/32 power-up and delivery state power-up state after power-up, the device is in the following state: C low power stand-by mode C deselected (after power-up, a falling edge is re- quired on chip select (s ) before any instruc- tions can be started). C not in the hold condition C the write enable latch (wel) is reset to 0 C write in progress (wip) is reset to 0 the bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). initial delivery state the device is delivered with the memory array set at all 1s (ffh). the block protect (bp1 and bp0) bits are initialized to 0.
17/32 m95040, m95020, m95010 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 6. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature C65 150 c t lead lead temperature during soldering pdip: 10 seconds so: 20 seconds (max) 1 tssop: 20 seconds (max) 1 260 235 235 c v o output voltage C0.3 v cc +0.6 v v i input voltage C0.3 6.5 v v cc supply voltage C0.3 6.5 v v esd electrostatic discharge voltage (human body model) 2 C4000 4000 v
m95040, m95020, m95010 18/32 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 7. operating conditions (m950x0) table 8. operating conditions (m950x0-w) table 9. operating conditions (m950x0-s) table 10. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. figure 16. ac measurement i/o waveform symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (range 6) C40 85 c ambient operating temperature (range 3) C40 125 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (range 6) C40 85 c ambient operating temperature (range 3) C40 125 c symbol parameter min. max. unit v cc supply voltage 1.8 3.6 v t a ambient operating temperature C20 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc
19/32 m95040, m95020, m95010 table 11. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 5 mhz. table 12. dc characteristics (m950x0, temperature range 6) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. table 13. dc characteristics (m950x0, temperature range 3) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (d) v in = 0v 8 pf input capacitance (other pins) v in = 0v 6 pf symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1 v cc /0.9. v cc at 5 mhz, v cc = 5 v, q = open 5ma i cc1 supply current (stand-by) s = v cc , v in = v ss or v cc , v cc = 5 v 10 a v il input low voltage C 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh 1 output high voltage i oh = C2 ma, v cc = 5 v 0.8 v cc v symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1 v cc /0.9. v cc at 5 mhz, v cc = 5 v, q = open 5ma i cc1 supply current (stand-by) s = v cc , v in = v ss or v cc , v cc = 5 v 10 a v il input low voltage C 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol 1 output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh 1 output high voltage i oh = C2 ma, v cc = 5 v 0.8 v cc v
m95040, m95020, m95010 20/32 table 14. dc characteristics (m950x0-w, temperature range 6) table 15. dc characteristics (m950x0-w, temperature range 3) table 16. dc characteristics (m950x0-s) note: 1. preliminary data, for the 1.8v to 3.6 supply voltage range devices. symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1 v cc /0.9. v cc at 2 mhz, v cc = 2.5 v, q = open 2ma i cc1 supply current (stand-by) s = v cc , v in = v ss or v cc , v cc = 2.5 v 2a v il input low voltage C 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 v v oh output high voltage i oh = C0.4 ma, v cc = 2.5 v 0.8 v cc v symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1 v cc /0.9. v cc at 2 mhz, v cc = 2.5 v, q = open 2ma i cc1 supply current (stand-by) s = v cc , v in = v ss or v cc , v cc = 2.5 v 5 a v il input low voltage C 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 v v oh output high voltage i oh = C0.4 ma, v cc = 2.5 v 0.8 v cc v symbol parameter test condition min. 1 max. 1 unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1 v cc /0.9. v cc at 1 mhz, v cc = 1.8 v, q = open 2ma i cc1 supply current (stand-by) s = v cc , v in = v ss or v cc , v cc = 1.8 v 2 a v il input low voltage C 0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = C0.1 ma, v cc = 1.8 v 0.8 v cc v
21/32 m95040, m95020, m95010 table 17. ac characteristics (m950x0, temperature range 6) note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. test conditions specified in table 10 and table 7 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch 1 t clh clock high time 90 ns t cl 1 t cll clock low time 90 ns t clch 2 t rc clock rise time 1 s t chcl 2 t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t chhl clock high set-up time before hold active 0 ns t chhh clock high set-up time before hold not active 0 ns t shqz 2 t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 50 ns t qhql 2 t fo output fall time 50 ns t hhqx 2 t lz hold high to output low-z 50 ns t hlqz 2 t hz hold low to output high-z 100 ns t w t wc write time 10 ms
m95040, m95020, m95010 22/32 table 18. ac characteristics (m950x0, temperature range 3) note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. test conditions specified in table 10 and table 7 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 100 ns t shch t css2 s not active setup time 100 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 100 ns t chsl s not active hold time 200 ns t ch 1 t clh clock high time 200 ns t cl 1 t cll clock low time 200 ns t clch 2 t rc clock rise time 1 s t chcl 2 t fc clock fall time 1 s t dvch t dsu data in setup time 40 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 100 ns t hlch clock low hold time after hold active 90 ns t chhl clock high set-up time before hold active 0 ns t chhh clock high set-up time before hold not active 0 ns t shqz 2 t dis output disable time 150 ns t clqv t v clock low to output valid 150 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 100 ns t qhql 2 t fo output fall time 100 ns t hhqx 2 t lz hold high to output low-z 100 ns t hlqz 2 t hz hold low to output high-z 150 ns t w t wc write time 10 ms
23/32 m95040, m95020, m95010 table 19. ac characteristics (m950x0-w, temperature ranges 6 and 3) note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. test conditions specified in table 10 and table 8 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 200 ns t shch t css2 s not active setup time 200 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 200 ns t chsl s not active hold time 200 ns t ch 1 t clh clock high time 200 ns t cl 1 t cll clock low time 200 ns t clch 2 t rc clock rise time 1 s t chcl 2 t fc clock fall time 1 s t dvch t dsu data in setup time 40 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 140 ns t hlch clock low hold time after hold active 90 ns t chhl clock high set-up time before hold active 0 ns t chhh clock high set-up time before hold not active 0 ns t shqz 2 t dis output disable time 250 ns t clqv t v clock low to output valid 150 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 100 ns t qhql 2 t fo output fall time 100 ns t hhqx 2 t lz hold high to output low-z 100 ns t hlqz 2 t hz hold low to output high-z 250 ns t w t wc write time 10 ms
m95040, m95020, m95010 24/32 table 20. ac characteristics (m950x0-s) note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. test conditions specified in table 10 and table 9 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 1 mhz t slch t css1 s active setup time 400 ns t shch t css2 s not active setup time 400 ns t shsl t cs s deselect time 300 ns t chsh t csh s active hold time 400 ns t chsl s not active hold time 400 ns t ch 1 t clh clock high time 400 ns t cl 1 t cll clock low time 400 ns t clch 2 t rc clock rise time 1 s t chcl 2 t fc clock fall time 1 s t dvch t dsu data in setup time 60 ns t chdx t dh data in hold time 100 ns t hhch clock low hold time after hold not active 350 ns t hlch clock low hold time after hold active 200 ns t chhl clock high set-up time before hold active 0 ns t chhh clock high set-up time before hold not active 0 ns t shqz 2 t dis output disable time 500 ns t clqv t v clock low to output valid 380 ns t clqx t ho output hold time 0 ns t qlqh 2 t ro output rise time 200 ns t qhql 2 t fo output fall time 200 ns t hhqx 2 t lz hold high to output low-z 250 ns t hlqz 2 t hz hold low to output high-z 500 ns t w t wc write time 10 ms
25/32 m95040, m95020, m95010 figure 17. serial input timing figure 18. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz
m95040, m95020, m95010 26/32 figure 19. output timing c q ai01449d s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
27/32 m95040, m95020, m95010 package mechanical pdip8 C 8 pin plastic dip, 0.25mm lead frame note: 1. drawing is not to scale. pdip8 C 8 pin plastic dip, 0.25mm lead frame pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 C C 0.100 C C ea 7.62 C C 0.300 C C eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150
m95040, m95020, m95010 28/32 so8 narrow C 8 lead plastic small outline, 150 mils body width note: drawing is not to scale. so8 narrow C 8 lead plastic small outline, 150 mils body width so-a e n cp b e a d c l a1 a 1 h h x 45? symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
29/32 m95040, m95020, m95010 tssop8 C 8 lead thin shrink small outline notes: 1. drawing is not to scale. tssop8 C 8 lead thin shrink small outline tssop8-m 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 a 0 8 0 8
m95040, m95020, m95010 30/32 part numbering table 21. ordering information scheme note: 1. temperature range available only on request. 2. the -s version (v cc range 1.8 v to 3.6 v) only available in temperature range 5. 3. all devices use a positive clock strobe: serial data in (d) is strobed on the rising edge of serial clock (c) and serial data out (q) is synchronized from the falling edge of serial clock (c). for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m95040 C w mn 6 tr device type m95 = spi serial access eeprom device function 3 040 = 4 kbit (512 x 8) 020 = 2 kbit (256 x 8) 010 = 1 kbit (128 x 8) operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v s 2 = v cc = 1.8 to 3.6v package bn = pdip8 (0.25 mm frame) mn = so8 (150 mil width) dw = tssop8 (169 mil width) temperature range 6 = C40 to 85 c 3 1 = C40 to 125 c 5 = C20 to 85 c option tr = tape & reel packing
31/32 m95040, m95020, m95010 revision history table 22. document revision history date rev. description of revision 10-may-2000 2.2 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the byte write operation 16-mar-2001 2.3 human body model meets jedec std (table 2). minor adjustments to figs 7,9,10,11 & tab 9. wording changes, according to the standard glossary illustrations and package mechanical data updated 19-jul-2001 2.4 temperature range 3 added to the -w supply voltage range in dc and ac characteristics 11-oct-2001 3.0 document reformatted using the new template 26-feb-2002 3.1 description of chip deselect after 8th clock pulse made more explicit
m95040, m95020, m95010 32/32 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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